(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method and structure for the creation of a 1T-RAM device that provides for process simplification, removes concerns of surface planarity and that allows for aggressive shrinkage of the cell size due to the manner in which a larger 1T-RAM cell capacitor is created.
(2) Description of the Prior Art
An important aspect of the creation of Dynamic Random Access Memory (DRAM) devices is the creation of the capacitive storage capability, whereby it is essential that storage node capacitor cell plates be large enough to retain an adequate voltage level without thereby being detrimentally affected by parasitic components of the structure or device noise that may be present during the operation of the device. Device performance improvements continue to be gained by reducing device dimensions, increasing the device density.
Typical DRAM storage cells are created comprising one single Metal-Oxide-Semiconductor Field-Effect-Transistor (MOS-FET) and a single capacitor, this DRAM storage cell is commonly referred to as a 1T-RAM device. The 1T-RAM device stores one bit of data on the capacitor as an electrical charge. Reductions in device dimensions and the therefrom following limitations in available surface area for the creation of the 1T-RAN capacitor create a serious obstacle to increasing the packaging density of DRAM devices. The problem of maintaining storage capacity while at the same time decreasing the 1T-RAM device dimensions remains a serious challenge in creating high-density 1T-RAM devices.
Using a two-dimensional stacked capacitor for the creation of a 64 MB DRAM cell, having a 1.5 xcexcm2 memory cell area, does not allow for the creation of the required capacitive storage capability. To address this problem, stacked capacitors have been proposed that make use of a three-dimensional structure in order to improve storage capacity. Variations of the stacked capacitor are for instance double stack, fin-structured, cylindrical, spread stacked and box structured capacitors.
In more recent applications, the planar capacitor has found increased use since the planar capacitor offers the advantage of being fully compatible in its creation with conventional logic device creation processes. The 1-T RAM cell size is however difficult to reduce when using the planar capacitor. A number of solutions have been suggested for this problem, the invention provides such a solution that allows for the use of a three-dimensional capacitor without requiring a large amount of surface area for the there-with created 1T-RAM cell.
U.S. Pat. No. 6,177,697 B1 (Cunningham) shows a capacitor and STI process.
U.S. Pat. No. 6,284,584 B1 (Hodges et al.) shows a process for a 1T memory.
U.S. Pat. No. 5,172,202(Kazuo et al.) discusses a 1T memory stacked cell capacitor.
A principal objective of the invention is to create a 1T-RAM cell by means of simplified processing procedures.
Another objective of the invention is to create a 1T-RAM cell without thereby experiencing issues of surface planarity of the created 1T-RAM cell.
Yet another objective of the invention is to create a 1T-RAM cell comprising an enlarged capacitor by expanding a dielectric surface area within the cell and by using this expanded surface area for the creation of the 1T-RAM capacitor.
A still further objective of the invention is to provide a method of creating a 1T-RAM cell that allows for easy shrinkage of the cell size.
In accordance with the objectives of the invention a new method and structure is provided for the creation of a 1T-RAM cell. Masking layers for Shallow Trench Isolation (STI) regions are provided over a layer of pad oxide over a substrate, the STI trenches are etched in the substrate, filled with field isolation oxide which is planarized. A 3D capacitor area is defined over the substrate, a layer of polysilicon or HSG polysilicon is deposited over exposed surfaces of the defined 3D capacitor and over the STI etch mask. A protective layer of photoresist or BARC is deposited over the layer of polysilicon or HSG polysilicon aligned with the 3D-capacitor area. The exposited layer of polysilicon or HSG polysilicon is removed, creating the bottom plate of a capacitor. The STI mask is removed, including the layer of pad oxide, exposing the substrate. SAC oxide is grown over the exposed substrate, n/p well impurity implants are performed into the substrate. The SAC oxide is removed, gate oxide is grown to form a layer of dielectric for CMOS gate electrodes and the capacitor dielectric. A layer of polysilicon is deposited, patterned and etched defining gate electrodes and capacitor upper plates. Back-End-Of-Line processing is then performed to complete the gate electrodes and to provide conductive interconnects to the gate electrodes and the capacitors.